Emerging multimedia and high-speed data applications are generating a demand for networks that are able to multiplex and switch a wide spectrum of data rates simultaneously. Asynchronous Transfer Mode (ATM) systems are widely recognized as the broadband integrated services digital network (B-ISDN) networking paradigm that will allow flexibility and efficiency in high-speed, multi-service, multimedia networks.
ATM is based on a fixed size connection-oriented cell switching methodology. An ATM cell is comprised of a well-defined and size-limited header area and user information area. The length of an ATM cell is 53 bytes, with a 5 byte header field and a 48 byte information field. The small fixed cell size and limited header functionality has an important influence on the design of an optimal ATM switching architecture. Many researchers have investigated the design of the core ATM switching fabric and a wide range of different switching architectures have been proposed in the last decade.
An ideal switch should provide fibre-like performance, meaning that it should provide low transmission delay and low bit error rate, and it should also be transparent to all users. Therefore, the principal function of an ATM switch is to transmit incoming cells to their destination addresses without incurring extra delays and excessive cell losses.
To date, only a few researchers have investigated the problems in constructing large scale switch architectures. As discussed in K.Y.Eng, M. J. Karol, Y. S. Yeh, "A Growable Packet (ATM) Switch Architecture: Design Principles and Applications", IEEE Trans. Commun., Vol.40, No.2, pp.423-430, Feb. 1992, various switches can be theoretically designed to large dimensions, but the technological and physical constraints (e.g. chip sizes, board sizes and speed of interconnects) often impose a practical limit on their maximum size. In order to build larger switching systems, two or more smaller switches have to be interconnected; however, the resulting complete architecture may no longer be the same as that of the individual switches because simple interconnection of the smaller switches creates several levels of queuing delay and results in severe performance degradation if congestion occurs at intermediate modules.
The major difficulty in implementing large scale switching networks is the cell synchronization within the network, which is mainly due to the complexity of interstage wiring. The drawback is that the length of interconnection wires between stages grows geometrically with respect to the size of the network, although the complexity of the hardware logic of each switching element remains the same. When the wires connected to the same switching element are not identical in length, there is a discrepancy in the cell arrival delay. As the switch network grows, the differences in wire lengths increases, thus compounding the problem of signal synchronization. As a result, cell synchronization due to differences in the length of interconnection wires represents a major difficulty in implementing high-speed networks.
The realization of large scale ATM switches has problems such as heat dissipation, power consumption and wire routing. Additionally, the speed of the output multiplexer and the speed of the switching elements represent other constraints. Moreover, the enormous number of required overlapping wires has precluded the implementation of the network on a single chip. This has caused researchers to find other ways of building a large network, such as the three-dimensional structure disclosed in D. Wilson, "A New Architecture for Packaging Wideband Communication Equipment Using a 3-D, Orthogonal Edge-to-Edge Topology", Proc. IEEE GLOBECOM '88, pp.430-434, 1988. Even though many space switch designs, such as those discussed in F. A. Tobagi, "Fast Packet Switch Architectures for Broadband Integrated Services Digital Networks", Proc. IEEE, Vol.78, No.1, pp.133-167, Jan., 1990, have a reasonable hardware complexity in terms of the number of 2.times.2 switching elements, many of the above-stated difficulties have been found in implementing high-speed multi-stage interconnection networks. Despite advances in ATM switch architectural designs, practical switch dimensions continue to be severely limited by both the technological and physical constraints of packaging.
Multipoint communication services are considered a basic functionality in ATM switches to meet future multimedia applications. A common method to achieve multicast services is to add a point-to-point switch at the back of a copy network. However, overflow problems in the copy network may result in problems; for example, head-of-the-line blocking exists even when an output queuing switch is used, and unfair services are provided to different output port.
In a multimedia environment, many different traffic types are statistically multiplexed and ATM cells can have different priority levels. To achieve priority sorting functionality, an additional sorting network can be used in input queuing or shared queuing switches. However, the priority requirement may conflict with the basic architectural designs in output queuing switches. For example, in the Knockout switch described in U.S. Pat. No. 4,760,570 issued Jul. 26, 1988 to Acampora et al. the N-input/L-output concentrator cannot let some cells with higher priority go to their output cells.
It is thus advantageous to provide a core switch fabric and an output controller for a fast packet switching system that permits the integration of multicast services and priority control into the switch design while at the same time providing a design that can readily be expanded with a minimum level of complexity.
It is also advantageous to provide a core switch fabric and output port controller which utilize a self-routing architecture so as to eliminate any need for central controlling means.
Further, it is advantageous to provide a core switch fabric and output port controller which can process any number of cell priority levels up to the limitation imposed by the size of the cell priority fields.
These advantages are included amongst those provided by the subject invention.